1. Field of the Invention
The present invention relates to a voltage regulator.
2. Description of the Related Art
A conventional voltage regulator is described. FIG. 4 is a circuit diagram illustrating a conventional voltage regulator.
NMOSs 46 and 47, PMOSs 48 and 49, NMOSs 53 and 54, a PMOS 52, and a PMOS 55 form a differential amplifier circuit. In the differential amplifier circuit, gates of the NMOSs 46 and 47 are input terminals while drains of the PMOS 55 and the NMOS 54 are output terminals. The PMOS 55 and NMOS 54 form a push-pull circuit. NMOSs 44 and 45 form a current mirror circuit and have constant current characteristics. A constant current circuit 58 and the NMOSs 44 and 45 function as a current supply means to the differential amplifier circuit.
Input voltage Vin which is power supply voltage is input to an input terminal 42. A PMOS 56 outputs to an output terminal 43 output voltage Vout which is controlled to be predetermined constant voltage based on the input voltage Vin and output voltage of the differential amplifier circuit. The output terminal 43 outputs the output voltage Vout which is controlled to be the predetermined constant voltage. The output voltage Vout of the output terminal 43 is input to a voltage divider circuit 57. The voltage divider circuit 57 divides the output voltage Vout and outputs divided voltage Vfb. The constant current circuit 58 supplies constant current Ibias to the differential amplifier circuit. A reference voltage circuit 59 applies reference voltage Vref to the gate of the NMOS 46. The reference voltage Vref and the divided voltage Vfb are input to the differential amplifier circuit. The differential amplifier circuit amplifies differential voltage Vdiff between the reference voltage Vref and the divided voltage Vfb, and outputs the output voltage Vout based on the differential voltage Vdiff. The differential amplifier circuit controls the output voltage Vout to be the predetermined constant voltage by controlling gate voltage of the PMOS 56 such that the reference voltage Vref and the divided voltage Vfb are equal to each other (see, for example, Japanese Patent Application Laid-open No. 2001-273042).
Here, characteristics of the PMOSs 48 and 49, the PMOS 52, and the PMOS 55 are the same, characteristics of the NMOSs 46 and 47 are the same, and a mirror ratio of the current mirror circuit of the NMOSs 53 and 54 is 1:1.
When the differential voltage Vdiff between the reference voltage Vref and the divided voltage Vfb is 0, gate voltage of the NMOS 46 and gate voltage of the NMOS 47 are the same, and drain current of the NMOS 46 and drain current of the NMOS 47 are the same. Therefore, the values of those drain currents and of drain currents of the PMOSs 48 and 49, the PMOS 52, and the PMOS 55 are the same, and values of drain currents of the NMOSs 53 and 54 are the same. Each drain current is half of drain current Itail of the NMOS 45.
Next, the drain currents of the respective transistors are described. FIGS. 5A and 5B are graphs illustrating the drain currents of the respective conventional transistors.
FIG. 5A illustrates a relationship between the differential voltage Vdiff and absolute values of the drain currents of the NMOSs 46 and 47 which are transistors in an input stage of the differential amplifier circuit. When the differential voltage Vdiff is 0, the values of the drain currents of the NMOSs 46 and 47 are the same, and each of the drain currents is half of the drain current Itail of the NMOS 45. When the differential voltage Vdiff varies, the absolute value of the drain current of one of the NMOSs 46 and 47 increases, and the absolute value of the drain current of the other MOS decreases accordingly.
FIG. 5B illustrates a relationship between the differential voltage Vdiff and absolute values of the drain currents of the PMOS 55 and the NMOS 54 (absolute values of charge and discharge currents with respect to a gate of the PMOS 56 which is an output transistor). When the differential voltage Vdiff is 0, the values of the drain currents of the PMOS 55 and the NMOS 54 are the same, and each of the drain currents is half of the drain current Itail of the NMOS 45.
When the differential voltage Vdiff varies, the absolute value of the drain current of one of the PMOS 55 and the NMOS 54 increases, and the absolute value of the drain current of the other MOS decreases accordingly. A maximum value Imax of the drain currents (charge and discharge currents with respect to gate of PMOS 56) is the value of the drain current Itail of the NMOS 45.
Power consumption of electronic equipment such as portable electronic equipment is sometimes reduced by switching an electronic circuit therein between two states: a standby state for operation with reduced power consumption; and a normal operation state other than the standby state. In such a case, power consumption of a voltage regulator for supplying power supply voltage to the electronic equipment may also be reduced.
However, in an ordinary voltage regulator, reduced power consumption results in inferior transient response characteristics.